Development of an Improved Frame Level Redundancy Scrubbing Algorithm for Static Random Access Memory Based Field Programmable Gate Array

Description

– Development of an Improved Frame Level Redundancy Scrubbing Algorithm for Static Random Access Memory Based Field Programmable Gate Array –

Download Development of an Improved Frame Level Redundancy Scrubbing Algorithm for Static Random Access Memory Based Field Programmable Gate Array. Electrical and Computer Engineering students who are writing their projects can get this material to aid their research work.

Abstract

The use of Static Random Access Memory (SRAM)-based Field Programmable Gate Array (FPGA) in critical applications has been considered a solution in the space and avionics domain due to its flexibility in achieving multiple requirements such as re-programmability and good performance.

However, SRAM-based FPGAs are susceptible to radiation-induced Single Event Upset (SEU) that affect the functionality of the implemented design.

This research presents the development of an improved Frame Level Redundancy (FLR) Scrubbing algorithm for SRAM-based FPGA to mitigate against radiation-induced SEU.

Introduction

Static random access memory (SRAM) based field-programmable gate arrays (FPGAs) are complementary metal-oxide-semiconductor (CMOS) devices with a special characteristic of reconfigurability making them desirable for use in systems with evolving technology (Jorge et al., 2015).

The use of FPGAs has been shown to provide high computational density and efficiency for many computing applications by allowing circuits to be customized to any application of interest (Wirthlin, 2015).

They are attractive to critical applications due to their high performance, power consumption, and reconfiguration capability (nonfat et al., 2015), and can be re-configured in the field, design updates can be performed while the device is still operational (kastensmidt & rech, 2016).

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